Model-based Design and Formal Analysis of Arbitration Protocols on Multiple-Bus Architecture

Multiple-Bus architectures for multiprocessors systems are preferred by manufacturers for implementation as they are providing higher bandwidth and more reliability than single bus architectures. The key notion in such a multiple-bus system is the bus arbitration strategy which resolves request con icts and allocates buses to requesting devices. Indeed, fast and fair bus arbitration gives higher throughput and less queuing time. In this paper we propose a high-level formal model of multiple-bus multiprocessor architecture seen as a component-based system. The proposed model o ers a way to easily implement, analyze and compare di erent arbitration protocols using a rich notion of connectors between components. This model allows to study relevant properties such as fairness and deadlock freedom at a high level of abstraction. Moreover, the proposed model of the studied protocols is modeled in a distributed manner which makes the generation of their implementation more interesting and the study of their performance e ciency more relevant.